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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 59: Configuration Switching Characteristics (Cont’d)
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
T MMCMDCK_DI /
T MMCMCKD_DI
T MMCMDCK_DEN /
T MMCMCKD_DEN
T MMCMDCK_DWE /
T MMCMCKD_DWE
T MMCMCKO_DO
T MMCMCKO_DRDY
DI Setup/Hold
DEN Setup/Hold time
DWE Setup/Hold time
CLK to out of DO (3)
CLK to out of DRDY
1.25/
0.00
1.25/
0.00
1.25/
0.00
2.60
0.32
1.40/
0.00
1.40/
0.00
1.40/
0.00
3.02
0.34
1.63/
0.00
1.63/
0.00
1.63/
0.00
3.64
0.38
1.64/
0.00
1.64/
0.00
1.64/
0.00
3.68
0.38
ns
ns
ns
ns
ns
Notes:
1.
2.
3.
To support longer delays in configuration, use the design solutions described in UG360 : Virtex-6 FPGA Configuration User Guide .
Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
DO will hold until next DRP operation.
Clock Buffers and Networks
Table 60: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
Description
Devices
-3
Speed Grade
-2 -1
-1L
Units
T BCCCK_CE /T BCCKC_CE (1)
T BCCCK_S /T BCCKC_S (1)
T BCCKO_O (2)
CE pins Setup/Hold
S pins Setup/Hold
BUFGCTRL delay from I0/I1 to O
All
All
All
0.11/
0.00
0.11/
0.00
0.07
0.13/
0.00
0.13/
0.00
0.08
0.16/
0.00
0.16/
0.00
0.10
0.13/
0.00
0.13/
0.00
0.10
ns
ns
ns
Maximum Frequency
F MAX
Global clock tree (BUFG)
All except LX760
LX760
800
N/A
750
700
700
700
667
667
MHz
MHz
Notes:
1.
2.
T BCCCK_CE and T BCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold
times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching
between clocks.
T BGCKO_O (BUFG delay from I0 to O) values are the same as T BCCKO_O values.
Table 61: Input/Output Clock Switching Characteristics (BUFIO)
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
T BIOCKO_O
Clock to out delay from I to O
0.14
0.16
0.18
0.21
ns
Maximum Frequency
F MAX
I/O clock tree (BUFIO)
800
800
710
710
MHz
Table 62: Regional Clock Switching Characteristics (BUFR)
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
T BRCKO_O
T BRCKO_O_BYP
Clock to out delay from I to O
Clock to out delay from I to O with Divide Bypass attribute
set
0.56
0.28
0.62
0.31
0.73
0.36
0.82
0.41
ns
ns
DS152 (v3.6) March 18, 2014
Product Specification
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